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| www.fairchildsemi.com FSD210B, FSD200B Features * Single Chip 700V Sense FET Power Switch for 7DIP * Precision Fixed Operating Frequency (134KHz) * FSD210B Consumes Under 0.1W at 265VAC & No Load with Advanced Burst-Mode Operation * Internal Start-up Circuit * Pulse-by-Pulse Current Limiting * Over Load Protection (OLP) * Internal Thermal Shutdown Function (TSD) * Auto-Restart Mode * Under Voltage Lockout (UVLO) with Hysteresis * Built-in Soft Start * Frequency Modultation for EMI Reduction * FSD200B Does Not Require an Auxiliary Bias Winding Green Mode Fairchild Power Switch (FPSTM) OUTPUT POWER TABLE PRODUCT FSD210B FSD200B FSD210BM FSD200BM 85-265VAC 230VAC 15%(3) Open Open (1) Adapter(1) Adapter Frame(2) Frame(2) 5W 7W 4W 5W 5W 7W 4W 5W 5W 7W 4W 5W 5W 7W 4W 5W Applications * Charger & Adapter for Mobile Phone, PDA & MP3 * Auxiliary Power for White Goods, PC, C-TV & Monitor Notes: 1. Typical continuous power in a non-ventilated enclosed adapter with sufficient drain pattern as a heat sinker, at 50C ambient. 2. Maximum practical continuous power in an open frame design with sufficient drain pattern as a heat sinker, at 50C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit AC IN Related Application Notes * AN-4137, 4141, 4147(Flyback) / AN-4134(Forward) / AN-4138(Charger) DC OUT Vstr Drain Description Each product in the FSD2x0B (x for 0, 1) family consists of an integrated Pulse Width Modulator (PWM) and Sense FET, and is specifically designed for high performance offline Switch Mode Power Supplies (SMPS) with minimal external components. Both devices are integrated high voltage power switching regulators which combine an avalanche rugged Sense FET with a current mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), an optimized gate turn-on/turn-off driver, Thermal Shut Down (TSD) protection and temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSD2x0B devices reduce total component count, design size, weight while increasing efficiency, productivity, and system reliability. Both devices provide a basic platform that is well suited for the design of cost-effective flyback converters. FPSTM is a trademark of Fairchild Semiconductor Corporation. (c)2005 Fairchild Semiconductor Corporation PWM Vfb Vcc Source Figure 1. Typical Flyback Application for FSD210B AC IN DC OUT Vstr PWM Vfb Drain Vcc Source Figure 2. Typical Flyback Application for FSD200B Rev.1.0.3 FSD210B, FSD200B Internal Block Diagram Vstr 8 Vcc 5 UVLO Voltage Ref Internal Bias 8.7/6.7V IDELAY 5uA L H 7 Drain IFB Frequency Modulation Vck OSC DRIVER S Q R SFET 250uA Vfb 4 V BURL/ V BURH BURST OLP Reset S R TSD LEB ILIM Q Vth Rsense VSD A/R S/S 3mS 1, 2, 3 GND Figure 3. Functional Block Diagram of FSD210B Vstr 8 Vcc 5 7V HV/REG UVLO Voltage Ref. INTERNAL BIAS ON/OFF 7 Drain IDELAY 5uA IFB Frequency Modulation Vck OSC DRIVER S Q R SFET 250uA Vfb 4 V BURL/ V BURH BURST OLP Reset S R TSD LEB ILIM Q Vth Rsense VSD A/R S/S 3mS 1, 2, 3 GND Figure 4. Functional Block Diagram of FSD200B 2 FSD210B, FSD200B Pin Definitions Pin Number 1, 2, 3 Pin Name GND Pin Function Description Sense FET source terminal on primary side and internal control ground. The feedback voltage pin is the inverting input to the PWM comparator and it has a normal input level between 0.5V and 2.5V. It has a 0.25mA current source connected internally while a capacitor and optocoupler are typically connected externally. A feedback voltage of 4.5V triggers over load protection (OLP). There is a time delay while charging external capacitor Cfb from 3V to 4.5V using an internal 5uA current source. This time delay prevents false triggering under transient conditions, but still allows the protection mechanism to operate under true overload conditions. 4 Vfb 5 Vcc 7 Drain 8 Vstr Pin Configuration 7DIP 7LSOP GND 1 GND 2 GND 3 Vfb 4 5 Vcc 8 Vstr 7 Drain Figure 5. Pin Configuration (Top View) 3 FSD210B, FSD200B Absolute Maximum Ratings (Ta=25C, unless otherwise specified) Characteristic Drain Pin Voltage Vstr Pin Voltage Total Power Dissipation Drain Pin Voltage Vstr Pin Voltage Total Power Dissipation Supply Voltage Feedback Voltage Range Supply Voltage Feedback Voltage Range FSD200B FSD210B 7LSOP 7DIP Symbol VDRAIN VSTR PD VDRAIN VSTR PD VCC VFB VCC VFB TJ TA TSTG Value 700 700 1.68 670 670 1.45 10 -0.3 to VCC 20 -0.3 to VSTOP Internally limited -25 to +85 -55 to +150 Unit V V W V V W V V V V C C C Operating Junction Temperature Operating Ambient Temperature Storage Temperature Thermal Impedance (Ta=25C, unless otherwise specified) Parameter 7DIP Junction-to-Ambient Thermal(1) Junction-to-Case Thermal 7LSOP Junction-to-Ambient Thermal(1) Junction-to-Case Thermal (2) (2) Symbol Value 74.07 60.44 22.00 86.02 27.72 Unit C/W C/W C/W C/W C/W JA(3) JA(4) JC JA(5) JC Note: 1. Free standing with no heatsink. / Measurement Condition : Just before junction temperature TJ enters into OTP. 2. Measured on the DRAIN pin close to plastic interface. 3. Soldered to 100mm2 copper clad. 4. Soldered to 300mm2 copper clad. 5. Without copper clad. - all items are tested with the standards JESD 51-2, 51-3 (SOP) and 51-10 (DIP). 4 FSD210B, FSD200B Electrical Characteristics (Ta = 25C unless otherwise specified) Parameter SENSE FET SECTION Zero-Gate-Voltage Drain Current Drain-Source On-State Resistance Rise Time Fall Time CONTROL SECTION Switching Frequency Switching Frequency Modulation Range Maximum Duty Cycle Minimum Duty Cycle UVLO Threshold Voltage (FSD200B) UVLO Threshold Voltage (FSD210B) Feedback Source Current Internal Soft Start Time BURST MODE SECTION VBURH Burst Mode Voltage PROTECTION SECTION Peak Current Limit Current Limit Delay Time (1) (1) Symbol IDSS RDS(ON) tr tf fOSC fMOD DMAX DMIN VSTART VSTOP VSTART VSTOP IFB tS/S Condition VDS=560V, VGS=0V Tj=25C, ID=25mA Tj=100C, ID=25mA VDS=325V, ID=50mA VDS=325V, ID=25mA Tj=25C Tj=25C VFB=3.5V VFB=GND After turn on After turn on VFB=GND Min. 126 60 0 6.3 5.3 8.0 6.0 0.22 0.58 0.5 0.275 125 4.0 200 Typ. 28 42 100 50 134 4 66 0 7 6 8.7 6.7 0.25 3 0.64 0.58 60 0.320 220 145 4.5 5 600 1 700 700 7 Max. 100 32 48 142 72 0 7.7 6.7 9.4 7.4 0.28 0.7 0.64 0.365 160 5.0 7 1.2 900 - Unit A ns ns KHz KHz % % V V V V mA ms V V mV A ns C V ns A A mA A A V V VBURL Tj=25C VBUR(HYS) Hysteresis ILIM tCLD TSD VSD tLEB IDELAY IOP ICH IOP ICH VSTR VCCREG VFB=4.0V (control part only),VCC=7V i/t=150mA/us Tj=25C Thermal Shutdown Temperature Shutdown Feedback Voltage Leading Edge Blanking Time Shutdown Delay Current TOTAL DEVICE SECTION (2) 3 20 - Operating Supply Current (FSD200B) Start-Up Charging Current (FSD200B) Operating Supply Current (FSD210B) Start-Up Charging Current (FSD210B) Vstr Supply Voltage Vcc Regulation Voltage (FSD200B) VCC=0V (control part only),VCC=11V VCC=0V VCC=0V Note: 1. These parameters, although guaranteed, are not 100% tested in production 2. These parameter is derived from characterization 5 FSD210B, FSD200B Comparison Between FSDH565 and FSD210B Function Soft-Start FSDH565 not applicable 3ms FSD210B FSD210B Advantages * Gradually increasing current limit during soft-start further reduces peak current and voltage stresses * Eliminates external components used for soft-start in most applications * Reduces or eliminates output overshoot * Smaller transformer * Reduced conducted EMI * Improves light load efficiency * Reduces power consumption at noload * Transformer audible noise reduction * Greater immunity to arcing provoked by dust, debris and other contaminants Switching Frequency Frequency Modulation Burst Mode Operation 100KHz not applicable not applicable 134KHz 4KHz Built into controller Drain Creepage at Package 1.02mm 3.56mm DIP 3.56mm LSOP 6 FSD210B, FSD200B Typical Performance Characteristics (Control Part) (These characteristic graphs are normalized at Ta = 25C) 1.2 1.0 Normalized Normalized -25 0 25 50 75 100 125 0.8 0.6 0.4 0.2 0.0 Temperature () 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Temperature () Switching Frequency (fOSC) vs. Ta Operating Supply Current (IOP) vs. Ta 1.2 1.0 Normalized Normalized -25 0 25 50 75 100 125 0.8 0.6 0.4 0.2 0.0 Temperature () 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Temperature () Peak Current Limit (ILIM) vs. Ta Feedback Source Current (IFB) vs. Ta 1.20 1.00 Normalized Normalized -25 0 25 50 75 100 125 0.80 0.60 0.40 0.20 0.00 Temperature () 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -25 0 25 50 75 100 125 Temperature () Start Threshold Voltage (VSTART) vs. Ta Stop Threshold Voltage (VSTOP) vs. Ta 7 FSD210B, FSD200B Typical Performance Characteristics (Continued) 1.2 1.0 Normalized Normalized -25 0 25 50 75 100 125 0.8 0.6 0.4 0.2 0.0 Temperature () 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Temperature () Vcc Regulation Voltage vs. Ta (for FSD200B) Shutdown Feedback Voltage (VSD) vs. Ta 1.4 1.2 Normalized Normalized -25 0 25 50 75 100 125 1.0 0.8 0.6 0.4 0.2 0.0 Temperature () 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 Temperature () Start Up Charging Current (ICH) vs. Ta (for FSD210B) Start Up Charging Current (ICH) vs. Ta (for FSD200B) 8 FSD210B, FSD200B Functional Description 1. Startup : At startup, the internal high voltage current source supplies the internal bias and charges the external Vcc capacitor as shown in Figure 7. In the case of the FSD210B, when Vcc reaches 8.7V the device starts switching and the internal high voltage current source is disabled. The device is in normal operation provided that Vcc does not drop below 6.7V. After startup the bias is supplied from the auxiliary transformer winding. In the case of FSD200B, An internal high voltage regulator (HV Req.) located between Vstr pin and Vcc pin regulates the Vcc to be 7V and supplies operating current, thus FSD200B needs no auxiliary bias winding. Calculating the Vcc capacitor is an important step to design with the FSD200B/210B. At initial start-up in the both devices, the maximum value of start operating current ISTART is about 100uA, which supplies current to UVLO and Vref Blocks. The charging current I Vcc of the Vcc capacitor is equal to ISTR - 100uA. After Vcc reaches the UVLO start voltage only the bias winding supplies Vcc current to device. When the bias winding voltage is not sufficient, the Vcc level decreases to the UVLO stop voltage. At this time Vcc oscillates. In order to prevent this oscillation it is recommended that the Vcc capacitor be chosen to have the value between 10uF and 47uF. Vin,dc ISTR Vstr Vcc L Vin,dc ISTR Vstr Vcc H 8.7V/ 6.7V HV Reg. 7V FSD210B FSD200B Figure 6. Internal Startup Circuit 2. Feedback Control : The FSD200B/210B are voltage mode controlled devices as shown in Figure 8. Usually, an opto-coupler and KA431 type voltage reference are used to implement the feedback network. The feedback voltage is compared with an internally generated sawtooth waveform. This directly controls the duty cycle. When the KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increases, the feedback voltage Vfb is pulled down and it reduces the duty cycle. This will happen when the input voltage increases or the output load decreases. Vin,dc ISTR IVCC = ISTR-ISTART IVCC = ISTR-ISTART Vstr J-FET ISTART Vcc 5uA Vref 0.25mA OSC Vo Vfb Cfb Vcc 4 + VFB R Gate driver UVLO Vref Vcc KA431 FSD2xx VSD OLP VSTART UVLO Vcc must not drop below VSTOP Figure 8. PWM and Feedback Circuit VSTOP Bias winding voltage t Figure 7. Charging Vcc Capacitor through Vstr 3. Leading Edge Blanking (LEB) : At the instant the internal Sense FET is turned on, the primary side capacitance and secondary side rectifier diode reverse recovery typically cause a high current spike through the Sense FET. Excessive voltage across the Rsense resistor leads to incorrect feedback operation in the current mode PWM control. To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the PWM comparator for a short time (tLEB) after the Sense FET is turned on. 9 FSD210B, FSD200B 4. Protection Circuit : The FSD200B/210B have 2 selfprotection functions : over load protection (OLP) and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, the reliability is improved without increasing cost. Once a fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage V STOP (6.7VFSD210B, 6V-FSD200B), the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage VSTART (8.7V-FSD210B, 7V-FSD200B), the device resumes its normal operation. In this manner, the auto-restart can alternately enable and disable the switching of the power Sense FET until the fault condition is eliminated. VFB Over Load Protection 4.5V 3V t12= CFBx(V(t2)-V(t1)) / IDELAY t1 t12 = C FB V ( t 2 ) - V ( t1 ) ; I DELAY t2 t I DELAY = 5 A , V ( t1 ) = 3V , V ( t 2 ) = 4 . 5V Figure 10. Over Load Protection (OLP) OSC 5uA 400uA Vfb 4 R + OLP S R Q GATE DRIVER Cfb S RESET 4.5V Q 4.2 Thermal Shutdown (TSD) : The Sense FET and the control IC are integrated, making it easier for the control IC to detect the temperature of the Sense FET. When the temperature exceeds approximately 145C, thermal shutdown is activated. TSD R A/R FSD2xxB OLP, TSD Protection Block Figure 9. Protection Block 4.1 Over Load Protection (OLP) : Overload is defined as the load current exceeding a pre-set level due to an unexpected event. In this situation, the protection circuit should be activated in order to protect the SMPS. However, even when the SMPS is operating normally, the over load protection (OLP) circuit can be activated during the load transition. In order to avoid this undesired operation, the OLP circuit is designed to be activated after a specified time to determine whether it is a transient situation or an overload situation. In conjunction with the Ipk current limit pin (if used) the current mode feedback path would limit the current in the Sense FET when the maximum PWM duty cycle is attained. If the output consumes more than this maximum power, the output voltage (Vo) decreases below its rating voltage. This reduces the current through the opto-coupler LED, which also reduces the opto-coupler transistor current, thus increasing the feedback voltage (VFB). If VFB exceeds 3V, the feedback input diode is blocked and the 5uA current source (IDELAY) starts to charge Cfb slowly up to Vcc. In this condition, VFB increases until it reaches 4.5V, when the switching operation is terminated as shown in Figure 10. The shutdown delay time is the time required to charge Cfb from 3V to 4.5V with 5uA current source. 5. Soft Start : FSD200B/210B has an internal soft start circuit that gradually increases current through the Sense FET as shown in Figure 11. The soft start time is 3msec in FSD200B/210B. I(A) 3ms 0.25A 0.2A 0.3A t Figure 11. Internal Soft Start 10 FSD210B, FSD200B 6. Burst operation : In order to minimize the power dissipation in standby mode, the FSD200B/210B enter burst mode operation. As the load decreases, the feedback voltage decreases. The device automatically enters burst mode when the feedback voltage drops below VBURL(0.58V). At this point switching stops and the output voltages start to drop. This causes the feedback voltage to rise. Once is passes VBURH(0.64V) switching starts again. The feedback voltage falls and the process repeats. Burst mode operation alternately enables and disables switching of the power MOSFET to reduce the switching loss in the standby mode. Drain Current ts fs=1/ts 138kHz 134kHz 130kHz 4ms t Vo Vo set Figure 13. Frequency Modulation Waveform V FB CISPR22Q(PK) CISPR22A(AV) 0.64V 0.58V Ids Vds t Amplitude(dBV) Frequency(MHz) Figure 14. FSDH0165 Full Range EMI scan(100kHz, no Frequency Modulation) with charger set OSC S 5uA 4 250uA R on/off Q GATE DRIVER CISPR22Q(PK) CISPR22A(AV) 0.64V /0.58V FSD2xxB Burst Operation Block Figure 12. Burst Operation Function 7. Frequency Modulation : Modulating the switching frequency of a switched power supply can reduce EMI by spreading the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. The amount of EMI reduction is directly related to the depth of the reference frequency. As can be seen in Figure 13, the frequency changes from 130KHz to 138KHz in 4ms for the FSD200B/210B. Frequency modulation allows the use of a cost effective inductor instead of an AC input mode choke to satisfy the requirements of world wide EMI limits. Amplitude(dBV) Vfb Frequency(MHz) Figure 15. FSD210B Full Range EMI scan(134kHz, with Frequency Modulation) with charger set 11 FSD210B, FSD200B Application Tips 1. Methods of Reducing Audible Noise Switching mode power converters have electronic and magnetic components, which generate audible noises when the operating frequency is in the range of 20~20,000 Hz. Even though they operate above 20 kHz, they can make noise depending on the load condition. Designers can employ several methods to reduce these noises. Here are three of these methods: Glue or Varnish The most common method involves using glue or varnish to tighten magnetic components. The motion of core, bobbin and coil and the chattering or magnetostriction of core can cause the transformer to produce audible noise. The use of rigid glue and varnish helps reduce the transformer noise. But, it also can crack the core. This is because sudden changes in the ambient temperature cause the core and the glue to expand or shrink in a different ratio according to the temperature. Ceramic Capacitor Using a film capacitor instead of a ceramic capacitor as a snubber capacitor is another noise reduction solution. Some dielectric materials show a piezoelectric effect depending on the electric field intensity. Hence, a snubber capacitor becomes one of the most significant sources of audible noise. It is considerable to use a zener clamp circuit instead of an RCD snubber for higher efficiency as well as lower audible noise. Adjusting Sound Frequency Moving the fundamental frequency of noise out of 2~4 kHz range is the third method. Generally, humans are more sensitive to noise in the range of 2~4 kHz. When the fundamental frequency of noise is located in this range, one perceives the noise as louder although the noise intensity level is identical. Refer to Figure 16. Equal Loudness Curves. When FPS acts in Burst mode and the Burst operation is suspected to be a source of noise, this method may be helpful. If the frequency of Burst mode operation lies in the range of 2~4 kHz, adjusting feedback loop can shift the Burst operation frequency. In order to reduce the Burst operation frequency, increase a feedback gain capacitor (CF), opto-coupler supply resistor (RD) and feedback capacitor (CB) and decrease a feedback gain resistor (RF) as shown in Figure 17. Typical Feedback Network of FPS. Figure 16. Equal Loudness Curves Figure 17. Typical Feedback Network of FPS 2. Other Reference Materials AN-4134: Design Guidelines for Off-line Forward Converters Using Fairchild Power Switch (FPSTM) AN-4137: Design Guidelines for Off-line Flyback Converters Using Fairchild Power Switch (FPS) AN-4138: Design Considerations for Battery Charger Using Green Mode Fairchild Power Switch (FPSTM) AN-4140: Transformer Design Consideration for Off-line Flyback Converters using Fairchild Power Switch (FPSTM) AN-4141: Troubleshooting and Design Tips for Fairchild Power Switch (FPSTM) Flyback Applications AN-4147: Design Guidelines for RCD Snubber of Flyback AN-4148: Audible Noise Reduction Techniques for FPS Applications 12 FSD210B, FSD200B Typical Application Circuit - 1 Application Cellular Phone Charger Output power 3.38W Input voltage Universal input (85-265Vac) Output voltage (Max current) 5.2V (650mA) Features * * * * * * High efficiency (>67% at Universal Input) Low zero load power consumption (<100mW at 240Vac) with FSD210B Low component count Enhanced system reliability through various protection functions Internal soft-start (3ms) Frequency Modulation for low EMI Key Design Notes * The constant voltage (CV) mode control is implemented with resistors R8, R9, R10 and R11, shunt regulator U2, feedback capacitor C9 and opto-coupler U3. * The constant current (CC) mode control is designed with resistors R8, R9, R15, R16, R17 and R19, NPN transistor Q1 and NTC TH1. When the voltage across current sensing resistors R15,R16 and R17 is 0.7V, the NPN transistor turns on and the current through the opto coupler LED increases. This reduces the feedback voltage and duty ratio. Therefore, the output voltage decreases and the output current is regulated. * The NTC(negative thermal coefficient) resistor is used to compensate the temperature characteristics of the transistor Q1. * The zener diodes (ZD1, ZD2) are used to bypass the ESD or surge. 1. Schematic C6 1.5nF-Y 250VAC R6 R7 4.7M 0.25W 4.7M 0.25W L1 330uH T1 FUSE 10R 1W D1 1N4007 D2 1N4007 R3 47k R1 4.7k R4 47k 1 C3 1nF 1kV 7 C7 330uF 16V R8 510R R9 56R D7 SB260 L3 3.9uH Vo (5.2V, 0.65A) R10 2.2K U3 H11A817A C9 470nF C8 330uF 16V AC AC 2 8 D3 1N4007 D4 1N4007 C1 4.7uF 400V C2 4.7uF 400V D5 UF4007 Q1 2N2222 C10 4.7uF 50V U2 TL431 R12 2K 7 Drain Vcc Vfb 5 4 H11A817B 4 D6 1N4148 R4 39R 3 TH1 10K R19 510R R13 300R R15 3R0 R16 3R0 R17 3R0 R14 150R 8 Vstr GND U1 FSD210 GND 2 For FSD21x C4 ZD1 100nF 19V C5 33uF 50V ZD2 19V 1 3 GND 13 FSD210B, FSD200B 2. Transformer Schematic Diagram 2mm 1 8 2mm 2 7 W4 W3 3 6 W2 W1 4 . CORE : EE1616 5 3. Winding Specification Pin(S F) W1 12 0.16x1 Wire Turns 99 Winding Method Solenoid winding Insulation : Polyester Tape t = 0.025mm, 2Layers W2 43 0.16x1 18 Center Solenoid winding Insulation : Polyester Tape t = 0.025mm, 2Layers W3 1 open 0.16x1 50 Solenoid winding Insulation : Polyester Tape t = 0.025mm, 3Layers W4 87 0.40x1 9 Solenoid winding Insulation : Polyester Tape t = 0.025mm, 3Layers 4. Electrical Characteristics P in In d u c ta n c e Leakage 1 2 1 2 Spec. 1 .6 m H 50 uH R e m a rk 1kH z, 1V 3 ,4 ,7 ,8 s h o rt 100KH z, 1V 5. Core & Bobbin Core : EER1616 Bobbin : EER1616 14 FSD210B, FSD200B Typical Application Circuit - 2 Application Non-Isolation Buck Output power 1.2W Input voltage DC 120 ~ 375V (for Universal Input) Output voltage (Max current) 12V (100mA) Features * Non-Isolation Buck converter * Low component count * Enhanced system reliability through various protection functions Key Design Notes * The output voltage(12V) is regulated with resistors R1, R2 and R3, zener diode D3, the transistor Q1 and the capacitor C2. While the FSD210B is off, diodes D1 and D2 are on. At this time the output voltage 12V is sensed by the feedback components listed above. * R 680K is used to prevent the OLP(over load protection) at startup. * R 8.2K is a dummy resistor to regulate output voltage in light load. 1. Schematic VINDC D2 Vcc Vfb GND 5 4 R2 110 D3(ZD) 1N759A UF4004 Drain GND 7 8 U1 FSD21x C1 4.7uF/400V Vstr GND R 680K D1 C2 47nF/50V Q1 R1 110 C5 47uF 50V 1 2 3 KSP2222A R3 750 L1 1mH C4 1000uF 16V R VOUT(12V/100mA) GND UF4004 8.2K GND 0 15 FSD210B, FSD200B Package Dimensions 7-DIP 16 FSD210B, FSD200B Package Dimensions (Continued) 7-LSOP 17 FSD210B, FSD200B Ordering Information Product Number FSD210B FSD200B FSD210BM FSD200BM Package 7DIP 7DIP 7LSOP 7LSOP Marking Code FSD210 FSD200 FSD210 FSD200 BVDSS 700V 700V 650V 650V fOSC 134KHz 134KHz 134KHz 134KHz RDS(ON) 28 28 28 28 DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 9/29/05 0.0m 001 (c) 2005 Fairchild Semiconductor Corporation 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. |
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